This invention relates to monolithic, large-scale integrated semiconductor circuit structures and particularly to chips containing level sensitive logic circuits.
In U.S. Pat. No. 3,783,254, entitled "Level Sensitive Logic System", Edward Eichelberger described a novel logic system of combinational networks and sequential circuits which permits both DC as well as AC testing of the logic system. This eliminates the need for special test points in such a system. Dynamic measurements of logic networks that are buried within a particular logic chip can be made without disturbing the state of the system.
In the Eichelberger system, the functional logic units are dependent solely on the occurrence of signals from a number of system clock trains. This is accomplished by using clocked D.C. latches for all internal storage circuitry in the general system logics. The latch circuitry is functionally partitioned along with associated combinational logic networks and arranged in sets. The plural clock trains are synchronous but non-overlapping and independent. The sets of latch circuitry are coupled through combinational logic to other sets of latches that are controlled by other system clock trains or combinations thereof.
In the preferred embodiment of the Eichelberger invention, each latch circuit includes additional circuitry so that each latch functions as a shift register latch (SRL) having input/output and shift controls which are independent of the system clocks and the system input/outputs. With this additional circuitry, all of the system clocks can be deactivated, isolating all of the latch circuits from one another, and permitting a scan-in/scan-out function to be performed. All of the sequential circuitry is thereby reduced to combinational circuitry which is partitioned down to the level of multistage combinational networks. This permits automatic test generation to be performed for testing functionally each circuit in the entire logical unit.
The SRL's are then employed to shift in any desired test pattern of binary ones and zero's where they are retained for use as input to the combinational networks. Results of the combinational logic are clocked into the latches and then shifted out to for measurement and comparison to determine the functional response of the logical unit.
In designing the architecture of logic circuitry on a semiconductor chip, the critical factors of power dissipation circuit type, physical layout and performance must be compromised to achieve low cost. Recently, the physical layout or architecture of the chip has begun to receive increased consideration. Once a circuit family, such as TTL, DTL, etc. has been chosen, the power dissipation is more or less fixed. The performance of the design, consisting of intracell and intercell delays, is also fixed both by the circuit family as well as the physical layout. Thus, the physical layout is the remaining factor over which the semiconductor structure or circuit designer has some control.
One example of a chip architecture, or layout, which is adaptable to incorporate level sensitive logic circuits is described in the application by E. E. Cass, Ser. No. 483,463 filed June 26, 1974 and assigned to the same assignee as the present application. In that layout, the cells are arranged in an orthogonal array, with the cells in substantially parallel rows in both orthogonal directions. In the preferred embodiment of the Cass invention, the cells are arranged in blocks which are two cells wide in the Y direction and four cells wide in the X direction. Each cell takes up substantially the same amount of chip area and has substantially the same layout configuration as every other cell. The chip layout features a regularly-structured matrix of logic gates exhibiting a nearly equal preference for data flow progression in both horizontal and vertical directions.
The Cass invention has been successful in reducing both the number of required metallization levels for intra-and intercell connections as well as the size of the cells as compared to prior art layouts. In addition, the "personalization" of the chip, i.e., the placement of the metallization wiring to define a specific chip circuit structure by computerized design automation, is substantially easier with the Cass layout than with previous designs. However, a significant amount of chip area is unused for active devices because of the space required by the metallization on the surface of the chip.